The present disclosure relates generally to integrated circuit chip, and more particularly to partition-able storage of chip test results using inactive storage elements during chip tests.
An integrated circuit chip (IC chip, or chip) may include normal functional circuits, such as arithmetic logic unit (ALU), floating-point unit (FPU), registers, scan latches, and memory. In order to ensure the quality of the chip, certain additional circuits are added to the chip for testing, repair, and test results logging. These circuits may include built-in self-test (BIST) engines, memory built-in self-test (MemBIST) engines, logic built-in self-test (LBIST) engines, and built-in self-repair (BISR) engines. Additional circuits, latches, and memory, such as failed logic registers and failed address registers, are typically added to the chip to store test results from these BIST engines. There is a trade-off as to how much of this information is retained on chip (costing chip area) before being extracted by the tester vs. extracting fail data more frequently with the tester (costing more test time, but less chip area). It is desirable to have a chip test scheme that requires minimal test time for chip testing and minimal chip area for storing chip test results.
Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.